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annotate src/insn_gen.c @ 8:f1df096aa76f 1.1
Tagged 1.1 bugfix release
| author | lost |
|---|---|
| date | Sun, 04 Jan 2009 05:46:07 +0000 |
| parents | 34568fab6058 |
| children | 74a3fef7c8d0 |
| rev | line source |
|---|---|
| 0 | 1 /* |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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2 insn_gen.c, Copyright © 2008 William Astle |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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3 |
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34568fab6058
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4 This file is part of LWASM. |
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34568fab6058
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5 |
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34568fab6058
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6 LWASM is free software: you can redistribute it and/or modify it under the |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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7 terms of the GNU General Public License as published by the Free Software |
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34568fab6058
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8 Foundation, either version 3 of the License, or (at your option) any later |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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9 version. |
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10 |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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11 This program is distributed in the hope that it will be useful, but WITHOUT |
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34568fab6058
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12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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14 more details. |
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15 |
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16 You should have received a copy of the GNU General Public License along with |
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34568fab6058
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17 this program. If not, see <http://www.gnu.org/licenses/>. |
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34568fab6058
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18 |
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34568fab6058
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19 Contains code for parsing general addressing modes (IMM+DIR+EXT+IND) |
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34568fab6058
Fixed package to include all required files; also added copyright preamble to all source files
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20 */ |
| 0 | 21 |
| 22 #include <ctype.h> | |
| 23 #include "lwasm.h" | |
| 24 #include "instab.h" | |
| 25 | |
| 26 extern void insn_indexed_aux(asmstate_t *as, sourceline_t *cl, char **optr, int *b1, int *b2, int *b3); | |
| 27 | |
| 28 void insn_gen_aux(asmstate_t *as, sourceline_t *cl, char **optr, int *b1, int *b2, int *b3, int *op) | |
| 29 { | |
| 30 *b1 = *b2 = *b3 = -1; | |
| 31 char *optr2; | |
| 32 int v1, tv, rval; | |
| 33 | |
| 34 optr2 = *optr; | |
| 35 while (*optr2 && !isspace(*optr2) && *optr2 != ',') optr2++ | |
| 36 ; | |
| 37 if (*optr2 != ',' && **optr != '[') | |
| 38 { | |
| 39 // not indexed | |
| 40 if (**optr == '<') | |
| 41 { | |
| 42 (*optr)++; | |
| 43 rval = eval_expr(as, cl, optr, &v1); | |
| 44 v1 = v1 & 0xffff; | |
| 45 tv = v1 - ((cl -> dpval) << 8); | |
| 46 if (tv < 0 || tv > 0xff) | |
| 47 { | |
| 48 errorp2(ERR_OVERFLOW); | |
| 49 } | |
| 50 v1 = v1 & 0xff; | |
| 51 goto ins_gen_dir; | |
| 52 } | |
| 53 else if (**optr == '>') | |
| 54 { | |
| 55 // extended mode | |
| 56 (*optr)++; | |
| 57 rval = eval_expr(as, cl, optr, &v1); | |
| 58 goto ins_gen_ext; | |
| 59 } | |
| 60 else | |
| 61 { | |
| 62 // eval expr and see how big it is | |
| 63 rval = eval_expr(as, cl, optr, &v1); | |
| 64 v1 = v1 & 0xFFFF; | |
| 65 | |
| 66 if (cl -> undef && as -> passnum == 1) | |
| 67 { | |
| 68 cl -> p1f16 = 1; | |
| 69 goto ins_gen_ext; | |
| 70 } | |
| 71 | |
| 72 tv = v1 - (cl -> dpval << 8); | |
| 73 | |
| 74 if (tv < 0 || tv > 0xff || cl -> p1f16) | |
| 75 goto ins_gen_ext; | |
| 76 else | |
| 77 { | |
| 78 v1 = v1 & 0xff; | |
| 79 goto ins_gen_dir; | |
| 80 } | |
| 81 } | |
| 82 return; | |
| 83 } | |
| 84 | |
| 85 *op = instab[cl -> opcode].ops[1]; | |
| 86 insn_indexed_aux(as, cl, optr, b1, b2, b3); | |
| 87 return; | |
| 88 | |
| 89 ins_gen_dir: | |
| 90 *op = instab[cl -> opcode].ops[0]; | |
| 91 // cl -> code_operlen = 1; | |
| 92 cl -> addrmode = OPER_DIR; | |
| 93 if ((v1 & 0xFFFF) > 0xff) | |
| 94 errorp2(ERR_OVERFLOW); | |
| 95 *b1 = (v1); | |
| 96 return; | |
| 97 | |
| 98 ins_gen_ext: | |
| 99 *op = instab[cl -> opcode].ops[2]; | |
| 100 // cl -> code_operlen = 2; | |
| 101 cl -> addrmode = OPER_EXT; | |
| 102 *b1 = (v1 >> 8); | |
| 103 *b2 = (v1 & 0xff); | |
| 104 return; | |
| 105 } | |
| 106 | |
| 107 void insn_gen(asmstate_t *as, sourceline_t *cl, char **optr) | |
| 108 { | |
| 109 int rval; | |
| 110 int v1; | |
| 111 int b1, b2, b3, op; | |
| 112 | |
| 113 if (**optr == '#') | |
| 114 { | |
| 115 // immediate mode has perterbations on instruction size | |
| 116 (*optr)++; | |
| 117 emitop(instab[cl -> opcode].ops[3]); | |
| 118 rval = eval_expr(as, cl, optr, &v1); | |
| 119 | |
| 120 switch (instab[cl -> opcode].instype) | |
| 121 { | |
| 122 case INSTYPE_GEN8: | |
| 123 case INSTYPE_IMM8: | |
| 124 cl -> addrmode = OPER_IMM8; | |
| 125 // cl -> code_operlen = 1; | |
| 126 emit(v1 & 0xff); | |
| 127 if (v1 < -128 || v1 > 255) | |
| 128 errorp2(ERR_OVERFLOW); | |
| 129 return; | |
| 130 | |
| 131 case INSTYPE_GEN: | |
| 132 cl -> addrmode = OPER_IMM16; | |
| 133 // cl -> code_operlen = 2; | |
| 134 emit(v1 >> 8); | |
| 135 emit(v1 & 0xff); | |
| 136 return; | |
| 137 | |
| 138 case INSTYPE_GEN32: | |
| 139 cl -> addrmode = OPER_IMM32; | |
| 140 // cl -> code_operlen = 4; | |
| 141 emit(v1 >> 24); | |
| 142 emit((v1 >> 16) & 0xff); | |
| 143 emit((v1 >> 8) & 0xff); | |
| 144 emit(v1 & 0xff); | |
| 145 return; | |
| 146 | |
| 147 default: | |
| 148 errorp1(ERR_BADOPER); | |
| 149 return; | |
| 150 | |
| 151 } | |
| 152 | |
| 153 return; | |
| 154 } | |
| 155 if (instab[cl -> opcode].instype == INSTYPE_IMM8) | |
| 156 { | |
| 157 errorp1(ERR_BADOPER); | |
| 158 return; | |
| 159 } | |
| 160 | |
| 161 insn_gen_aux(as, cl, optr, &b1, &b2, &b3, &op); | |
| 162 emitop(op); | |
| 163 if (b1 != -1) | |
| 164 emit(b1); | |
| 165 if (b2 != -1) | |
| 166 emit(b2); | |
| 167 if (b3 != -1) | |
| 168 emit(b3); | |
| 169 } |