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Fix code generation error in gcc6809 It turned out that under some circumstances, the gcc optimizer would select an instruction sequence that had the sense of a branch inverted. It seems this was due to a particular instruction pattern included in the machine description not being quite right with respect to how the condition codes were tracked. Removing that instruction pattern seems to fix things (subtraction with the arguments reversed). gcc seems to be smart enough to figure out how to reorganize code to work without this reversed sense subtraction and then do the right thing.
author William Astle <lost@l-w.ca>
date Thu, 24 Mar 2016 20:07:20 -0600
parents e95f07cbce4e
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>2.4. Motorola S-Record</A
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>This ASCII format consists of a series of CR+LF terminated "records" of ASCII
text. Each record has the following structure: a start-of-record character
"S", an ASCII record type digit (0-9), a two-digit ASCII hex byte count, a 
four-digit ASCII hex address, an optional sequence of two-digit ASCII hex data
values, and a two-digit ASCII hex checksum. The LW tool chain issues only S0, 
S1, S5 and S9 record types. S1 records are limited to maximum of 16 data bytes
in length, and  paragraph alignment of addresses is favored. The address
sequence of the S-Records directly follows that of the source file; multiple
ORG directives in the source code may result in out-of-sequence addresses in
the S-Record output. </P
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>Motorola S-Record format is a standard ASCII format accepted by most memory
device programming equipment. It is particularly useful when the assembled 
code output is destined to reside within an EPROM or Flash memory device,
for example.</P
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>LWASM can output this format since version 4.10. LWLINK can output this format
since version 4.11.</P
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