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Fix code generation error in gcc6809 It turned out that under some circumstances, the gcc optimizer would select an instruction sequence that had the sense of a branch inverted. It seems this was due to a particular instruction pattern included in the machine description not being quite right with respect to how the condition codes were tracked. Removing that instruction pattern seems to fix things (subtraction with the arguments reversed). gcc seems to be smart enough to figure out how to reorganize code to work without this reversed sense subtraction and then do the right thing.
author William Astle <lost@l-w.ca>
date Thu, 24 Mar 2016 20:07:20 -0600
parents b30091890d62
children
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>2.5. Intel Hex</A
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>This ASCII format consists of a series of CR+LF terminated "records" of ASCII
text. Each record has the following structure: a start-of-record character
":", a two-digit ASCII hex byte count, a four-digit ASCII hex address, a two-
digit ASCII hex record type, an optional sequence of two-digit ASCII hex data 
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and 01 Intel Hex record types. Data records are limited to maximum of 16 
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address sequence of the Intel hex records directly follows that of the source 
file; multiple ORG directives in the source code may result in out-of-sequence 
addresses in the Intel Hex output. </P
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>Intel Hex format is the other standard ASCII format accepted by most memory 
device programming equipment, it and the Motorola S-Record format are used for
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>LWASM can output this format since version 4.10.</P
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