view docs/manual/x41.html @ 396:d0c0fede5021

Update to gcc6809lw patch which may help compilation of some sources Due to persistent random compiler crashes and errors related to "M_REGS", this patch update (4.6.4-2) essentially removes the varius constraints allowing the "soft registers" in most operations. It was causing more problems than it solved and it is not clear that the logic behind those soft registers even makes sense any more. This patch also fixes a bogus comparison related to selecting the right size for a constant. Instead of the excessively clever comparison scheme that was previously in use, the comparisons have been replaced with straight forward comparisions for the top and bottom of the relevant 2's complement ranges.
author William Astle <lost@l-w.ca>
date Mon, 20 Jul 2015 22:32:41 -0600
parents b30091890d62
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>2.5. Intel Hex</A
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>This ASCII format consists of a series of CR+LF terminated "records" of ASCII
text. Each record has the following structure: a start-of-record character
":", a two-digit ASCII hex byte count, a four-digit ASCII hex address, a two-
digit ASCII hex record type, an optional sequence of two-digit ASCII hex data 
values, and a two-digit ASCII hex checksum. The LW tool chain issues only 00, 
and 01 Intel Hex record types. Data records are limited to maximum of 16 
data bytes in length, and paragraph alignment of addresses is favored. The 
address sequence of the Intel hex records directly follows that of the source 
file; multiple ORG directives in the source code may result in out-of-sequence 
addresses in the Intel Hex output. </P
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>Intel Hex format is the other standard ASCII format accepted by most memory 
device programming equipment, it and the Motorola S-Record format are used for
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>LWASM can output this format since version 4.10.</P
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