Mercurial > hg-old > index.cgi
annotate src/instab.c @ 104:2ba8f9ef1417
Added ifdef/ifndef conditionals
author | lost |
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date | Sun, 25 Jan 2009 04:02:50 +0000 |
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0 | 1 /* |
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2 instab.c |
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3 Copyright © 2008 William Astle |
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4 |
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5 This file is part of LWASM. |
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6 |
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7 LWASM is free software: you can redistribute it and/or modify it under the |
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8 terms of the GNU General Public License as published by the Free Software |
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9 Foundation, either version 3 of the License, or (at your option) any later |
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10 version. |
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11 |
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12 This program is distributed in the hope that it will be useful, but WITHOUT |
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13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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15 more details. |
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16 |
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17 You should have received a copy of the GNU General Public License along with |
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18 this program. If not, see <http://www.gnu.org/licenses/>. |
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19 |
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20 |
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21 Contains the instruction table for assembling code |
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22 */ |
0 | 23 |
24 #include <stdlib.h> | |
25 | |
26 #define __instab_c_seen__ | |
27 #include "instab.h" | |
28 | |
25
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29 extern OPFUNC(insn_inh); |
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30 extern OPFUNC(insn_gen8); |
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31 extern OPFUNC(insn_gen16); |
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32 extern OPFUNC(insn_gen32); |
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33 extern OPFUNC(insn_gen0); |
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34 extern OPFUNC(insn_rtor); |
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35 extern OPFUNC(insn_imm8); |
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36 extern OPFUNC(insn_rel8); |
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37 extern OPFUNC(insn_rel16); |
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38 extern OPFUNC(insn_rlist); |
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39 extern OPFUNC(insn_bitbit); |
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40 extern OPFUNC(insn_logicmem); |
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41 extern OPFUNC(insn_tfm); |
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42 extern OPFUNC(insn_indexed); |
50 | 43 |
47
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44 extern OPFUNC(pseudo_org); |
50 | 45 extern OPFUNC(pseudo_equ); |
46 extern OPFUNC(pseudo_rmb); | |
53 | 47 extern OPFUNC(pseudo_rmd); |
48 extern OPFUNC(pseudo_rmq); | |
49 extern OPFUNC(pseudo_zmb); | |
50 extern OPFUNC(pseudo_zmd); | |
51 extern OPFUNC(pseudo_zmq); | |
52 | 52 extern OPFUNC(pseudo_include); |
54
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53 extern OPFUNC(pseudo_end); |
56 | 54 extern OPFUNC(pseudo_align); |
55 extern OPFUNC(pseudo_error); | |
56 extern OPFUNC(pseudo_fcc); | |
57 extern OPFUNC(pseudo_fcs); | |
58 extern OPFUNC(pseudo_fcn); | |
59 extern OPFUNC(pseudo_fcb); | |
60 extern OPFUNC(pseudo_fdb); | |
61 extern OPFUNC(pseudo_fqb); | |
57 | 62 extern OPFUNC(pseudo_ifne); |
63 extern OPFUNC(pseudo_ifeq); | |
64 extern OPFUNC(pseudo_ifgt); | |
65 extern OPFUNC(pseudo_ifge); | |
66 extern OPFUNC(pseudo_iflt); | |
67 extern OPFUNC(pseudo_ifle); | |
68 extern OPFUNC(pseudo_else); | |
69 extern OPFUNC(pseudo_endc); | |
70 extern OPFUNC(pseudo_macro); | |
71 extern OPFUNC(pseudo_endm); | |
65
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72 extern OPFUNC(pseudo_setdp); |
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73 extern OPFUNC(pseudo_set); |
73 | 74 extern OPFUNC(pseudo_section); |
75 extern OPFUNC(pseudo_endsection); | |
76 extern OPFUNC(pseudo_pragma); | |
77 extern OPFUNC(pseudo_starpragma); | |
82 | 78 extern OPFUNC(pseudo_extern); |
90 | 79 extern OPFUNC(pseudo_export); |
104 | 80 extern OPFUNC(pseudo_ifdef); |
81 extern OPFUNC(pseudo_ifndef); | |
90 | 82 |
0 | 83 instab_t instab[] = |
84 { | |
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85 { "abx", { 0x3a, -0x1, -0x1, -0x1 }, insn_inh }, |
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86 { "adca", { 0x99, 0xa9, 0xb9, 0x89 }, insn_gen8 }, |
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87 { "adcb", { 0xd9, 0xe9, 0xf9, 0xc9 }, insn_gen8 }, |
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88 { "adcd", { 0x1099, 0x10a9, 0x10b9, 0x1089 }, insn_gen16 }, |
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89 { "adcr", { 0x1031, -0x1, -0x1, -0x1 }, insn_rtor }, |
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90 { "adda", { 0x9b, 0xab, 0xbb, 0x8b }, insn_gen8 }, |
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91 { "addb", { 0xdb, 0xeb, 0xfb, 0xcb }, insn_gen8 }, |
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92 { "addd", { 0xd3, 0xe3, 0xf3, 0xc3 }, insn_gen16 }, |
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93 { "adde", { 0x119b, 0x11ab, 0x11bb, 0x118b }, insn_gen8 }, |
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94 { "addf", { 0x11db, 0x11eb, 0x11fb, 0x11cb }, insn_gen8 }, |
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95 { "addr", { 0x1030, -0x1, -0x1, -0x1 }, insn_rtor }, |
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96 { "addw", { 0x109b, 0x10ab, 0x10bb, 0x108b }, insn_gen16 }, |
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97 { "aim", { 0x02, 0x62, 0x72, -0x1 }, insn_logicmem }, |
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98 { "anda", { 0x94, 0xa4, 0xb4, 0x84 }, insn_gen8 }, |
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99 { "andb", { 0xd4, 0xe4, 0xf4, 0xc4 }, insn_gen8 }, |
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100 { "andcc", { 0x1c, -0x1, -0x1, 0x1c }, insn_imm8 }, |
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101 { "andd", { 0x1094, 0x10a4, 0x10b4, 0x1084 }, insn_gen16 }, |
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102 { "andr", { 0x1034, -0x1, -0x1, -0x1 }, insn_rtor }, |
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103 { "asl", { 0x08, 0x68, 0x78, -0x1 }, insn_gen0 }, |
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104 { "asla", { 0x48, -0x1, -0x1, -0x1 }, insn_inh }, |
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105 { "aslb", { 0x58, -0x1, -0x1, -0x1 }, insn_inh }, |
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106 { "asld", { 0x1048, -0x1, -0x1, -0x1 }, insn_inh }, |
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107 { "asr", { 0x07, 0x67, 0x77, -0x1 }, insn_gen0 }, |
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108 { "asra", { 0x47, -0x1, -0x1, -0x1 }, insn_inh }, |
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109 { "asrb", { 0x57, -0x1, -0x1, -0x1 }, insn_inh }, |
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110 { "asrd", { 0x1047, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 111 |
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112 { "band", { 0x1130, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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113 { "bcc", { 0x24, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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114 { "bcs", { 0x25, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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115 { "beor", { 0x1134, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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116 { "beq", { 0x27, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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117 { "bge", { 0x2c, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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118 { "bgt", { 0x2e, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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119 { "bhi", { 0x22, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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120 { "bhs", { 0x24, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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121 { "biand", { 0x1131, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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122 { "bieor", { 0x1135, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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123 { "bior", { 0x1133, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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124 { "bita", { 0x95, 0xa5, 0xb5, 0x85 }, insn_gen8 }, |
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125 { "bitb", { 0xd5, 0xe5, 0xf5, 0xc5 }, insn_gen8 }, |
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126 { "bitd", { 0x1095, 0x10a5, 0x10b5, 0x1085 }, insn_gen16 }, |
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127 { "bitmd", { 0x113c, -0x1, -0x1, 0x113c }, insn_imm8 }, |
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128 { "ble", { 0x2f, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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129 { "blo", { 0x25, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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130 { "bls", { 0x23, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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131 { "blt", { 0x2d, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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132 { "bmi", { 0x2b, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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133 { "bne", { 0x26, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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134 { "bor", { 0x1132, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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135 { "bpl", { 0x2a, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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136 { "bra", { 0x20, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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137 { "brn", { 0x21, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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138 { "bsr", { 0x8d, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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139 { "bvc", { 0x28, -0x1, -0x1, -0x1 }, insn_rel8 }, |
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140 { "bvs", { 0x29, -0x1, -0x1, -0x1 }, insn_rel8 }, |
0 | 141 |
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142 { "clr", { 0x0f, 0x6f, 0x7f, -0x1 }, insn_gen0 }, |
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143 { "clra", { 0x4f, -0x1, -0x1, -0x1 }, insn_inh }, |
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144 { "clrb", { 0x5f, -0x1, -0x1, -0x1 }, insn_inh }, |
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145 { "clrd", { 0x104f, -0x1, -0x1, -0x1 }, insn_inh }, |
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146 { "clre", { 0x114f, -0x1, -0x1, -0x1 }, insn_inh }, |
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147 { "clrf", { 0x115f, -0x1, -0x1, -0x1 }, insn_inh }, |
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148 { "clrw", { 0x105f, -0x1, -0x1, -0x1 }, insn_inh }, |
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149 { "cmpa", { 0x91, 0xa1, 0xb1, 0x81 }, insn_gen8 }, |
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150 { "cmpb", { 0xd1, 0xe1, 0xf1, 0xc1 }, insn_gen8 }, |
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151 { "cmpd", { 0x1093, 0x10a3, 0x10b3, 0x1083 }, insn_gen16 }, |
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152 { "cmpe", { 0x1191, 0x11a1, 0x11b1, 0x1181 }, insn_gen8 }, |
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153 { "cmpf", { 0x11d1, 0x11e1, 0x11f1, 0x11c1 }, insn_gen8 }, |
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154 { "cmpr", { 0x1037, -0x1, -0x1, -0x1 }, insn_rtor }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
155 { "cmps", { 0x119c, 0x11ac, 0x11bc, 0x118c }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
156 { "cmpu", { 0x1193, 0x11a3, 0x11b3, 0x1183 }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
157 { "cmpw", { 0x1091, 0x10a1, 0x10b1, 0x1081 }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
158 { "cmpx", { 0x9c, 0xac, 0xbc, 0x8c }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
159 { "cmpy", { 0x109c, 0x10ac, 0x10bc, 0x108c }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
160 { "com", { 0x03, 0x63, 0x73, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
161 { "coma", { 0x43, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
162 { "comb", { 0x53, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
163 { "comd", { 0x1043, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
164 { "come", { 0x1143, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
165 { "comf", { 0x1153, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
166 { "comw", { 0x1053, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
167 { "cwai", { 0x3c, -0x1, -0x1, -0x1 }, insn_imm8 }, |
0 | 168 |
25
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
169 { "daa", { 0x19, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
170 { "dec", { 0x0a, 0x6a, 0x7a, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
171 { "deca", { 0x4a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
172 { "decb", { 0x5a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
173 { "decd", { 0x104a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
174 { "dece", { 0x114a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
175 { "decf", { 0x115a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
176 { "decw", { 0x105a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
177 { "divd", { 0x118d, 0x119d, 0x11ad, 0x11bd }, insn_gen8 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
178 { "divq", { 0x118e, 0x119e, 0x11ae, 0x11be }, insn_gen16 }, |
0 | 179 |
25
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
180 { "eim", { 0x05, 0x65, 0x75, -0x1 }, insn_logicmem }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
181 { "eora", { 0x98, 0xa8, 0xb8, 0x88 }, insn_gen8 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
182 { "eorb", { 0xd8, 0xe9, 0xf9, 0xc8 }, insn_gen8 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
183 { "eord", { 0x1098, 0x10a8, 0x10b8, 0x1088 }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
184 { "eorr", { 0x1036, -0x1, -0x1, -0x1 }, insn_rtor }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
185 { "exg", { 0x1e, -0x1, -0x1, -0x1 }, insn_rtor }, |
0 | 186 |
25
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
187 { "inc", { 0x0c, 0x6c, 0x7c, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
188 { "inca", { 0x4c, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
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189 { "incb", { 0x5c, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
190 { "incd", { 0x104c, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
191 { "ince", { 0x114c, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
192 { "incf", { 0x115c, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
193 { "incw", { 0x105c, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 194 |
25
3b818f05dc2a
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parents:
4
diff
changeset
|
195 { "jmp", { 0x0e, 0x6e, 0x7e, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
196 { "jsr", { 0x9d, 0xad, 0xbd, -0x1 }, insn_gen0 }, |
0 | 197 |
25
3b818f05dc2a
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parents:
4
diff
changeset
|
198 { "lbcc", { 0x1024, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
199 { "lbcs", { 0x1025, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
200 { "lbeq", { 0x1027, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
201 { "lbge", { 0x102c, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
202 { "lbgt", { 0x102e, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
203 { "lbhi", { 0x1022, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
204 { "lbhs", { 0x1024, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
205 { "lble", { 0x102f, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
206 { "lblo", { 0x1025, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
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207 { "lbls", { 0x1023, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
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208 { "lblt", { 0x102d, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
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209 { "lbmi", { 0x102b, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
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210 { "lbne", { 0x1026, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
211 { "lbpl", { 0x102a, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
212 { "lbra", { 0x16, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
213 { "lbrn", { 0x1021, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
214 { "lbsr", { 0x17, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
215 { "lbvc", { 0x1028, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
216 { "lbvs", { 0x1029, -0x1, -0x1, -0x1 }, insn_rel16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
217 { "lda", { 0x96, 0xa6, 0xb6, 0x86 }, insn_gen8 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
218 { "ldb", { 0xd6, 0xe6, 0xf6, 0xc6 }, insn_gen8 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
219 { "ldbt", { 0x1136, -0x1, -0x1, -0x1 }, insn_bitbit }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
220 { "ldd", { 0xdc, 0xec, 0xfc, 0xcc }, insn_gen16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
221 { "lde", { 0x1196, 0x11a6, 0x11b6, 0x1186 }, insn_gen8 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
222 { "ldf", { 0x11d6, 0x11e6, 0x11f6, 0x11c6 }, insn_gen8 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
223 { "ldq", { 0x10dc, 0x10ec, 0x10fc, 0xcd }, insn_gen32 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
224 { "lds", { 0x10de, 0x10ee, 0x10fe, 0x10ce }, insn_gen16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
225 { "ldu", { 0xde, 0xee, 0xfe, 0xce }, insn_gen16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
226 { "ldw", { 0x1096, 0x10a6, 0x10b6, 0x1086 }, insn_gen16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
227 { "ldx", { 0x9e, 0xae, 0xbe, 0x8e }, insn_gen16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
228 { "ldy", { 0x109e, 0x10ae, 0x10be, 0x108e }, insn_gen16 }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
229 { "ldmd", { 0x113d, -0x1, -0x1, 0x113d }, insn_imm8 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
230 { "leas", { 0x32, -0x1, -0x1, -0x1 }, insn_indexed }, |
3b818f05dc2a
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parents:
4
diff
changeset
|
231 { "leau", { 0x33, -0x1, -0x1, -0x1 }, insn_indexed }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
232 { "leax", { 0x30, -0x1, -0x1, -0x1 }, insn_indexed }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
233 { "leay", { 0x31, -0x1, -0x1, -0x1 }, insn_indexed }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
234 { "lsl", { 0x08, 0x68, 0x78, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
235 { "lsla", { 0x48, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
236 { "lslb", { 0x58, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
237 { "lsld", { 0x1048, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
238 { "lsr", { 0x04, 0x64, 0x74, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
239 { "lsra", { 0x44, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
240 { "lsrb", { 0x54, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
241 { "lsrd", { 0x1044, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
242 { "lsrw", { 0x1054, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 243 |
25
3b818f05dc2a
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parents:
4
diff
changeset
|
244 { "mul", { 0x3d, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
245 { "muld", { 0x118f, 0x119f, 0x11af, 0x11bf }, insn_gen16 }, |
0 | 246 |
25
3b818f05dc2a
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parents:
4
diff
changeset
|
247 { "neg", { 0x00, 0x60, 0x70, -0x1 }, insn_gen0 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
248 { "nega", { 0x40, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
249 { "negb", { 0x50, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
250 { "negd", { 0x1040, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
251 { "nop", { 0x12, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 252 |
25
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
253 { "oim", { 0x01, 0x61, 0x71, -0x1 }, insn_logicmem }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
254 { "ora", { 0x9a, 0xaa, 0xba, 0x8a }, insn_gen8 }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
255 { "orb", { 0xda, 0xea, 0xfa, 0xca }, insn_gen8 }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
256 { "orcc", { 0x1a, -0x1, -0x1, 0x1a }, insn_imm8 }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
257 { "ord", { 0x109a, 0x10aa, 0x10ba, 0x108a }, insn_gen16 }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
258 { "orr", { 0x1035, -0x1, -0x1, -0x1 }, insn_rtor }, |
0 | 259 |
25
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
260 { "pshs", { 0x34, -0x1, -0x1, -0x1 }, insn_rlist }, |
3b818f05dc2a
imported instruction table from older version to development version
lost
parents:
4
diff
changeset
|
261 { "pshsw", { 0x1038, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
262 { "pshu", { 0x36, -0x1, -0x1, -0x1 }, insn_rlist }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
263 { "pshuw", { 0x103a, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
264 { "puls", { 0x35, -0x1, -0x1, -0x1 }, insn_rlist }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
265 { "pulsw", { 0x1039, -0x1, -0x1, -0x1 }, insn_inh }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
266 { "pulu", { 0x37, -0x1, -0x1, -0x1 }, insn_rlist }, |
3b818f05dc2a
imported instruction table from older version to development version
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parents:
4
diff
changeset
|
267 { "puluw", { 0x103b, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 268 |
25
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269 { "rol", { 0x09, 0x69, 0x79, -0x1 }, insn_gen0 }, |
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270 { "rola", { 0x49, -0x1, -0x1, -0x1 }, insn_inh }, |
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271 { "rolb", { 0x59, -0x1, -0x1, -0x1 }, insn_inh }, |
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272 { "rold", { 0x1049, -0x1, -0x1, -0x1 }, insn_inh }, |
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273 { "rolw", { 0x1059, -0x1, -0x1, -0x1 }, insn_inh }, |
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274 { "ror", { 0x06, 0x66, 0x76, -0x1 }, insn_gen0 }, |
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275 { "rora", { 0x46, -0x1, -0x1, -0x1 }, insn_inh }, |
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276 { "rorb", { 0x56, -0x1, -0x1, -0x1 }, insn_inh }, |
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277 { "rord", { 0x1046, -0x1, -0x1, -0x1 }, insn_inh }, |
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278 { "rorw", { 0x1056, -0x1, -0x1, -0x1 }, insn_inh }, |
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279 { "rti", { 0x3b, -0x1, -0x1, -0x1 }, insn_inh }, |
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280 { "rts", { 0x39, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 281 |
25
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282 { "sbca", { 0x92, 0xa2, 0xb2, 0x82 }, insn_gen8 }, |
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283 { "sbcb", { 0xd2, 0xe2, 0xf2, 0xc2 }, insn_gen8 }, |
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284 { "sbcd", { 0x1092, 0x10a2, 0x10b2, 0x1082 }, insn_gen16 }, |
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285 { "sbcr", { 0x1033, -0x1, -0x1, -0x1 }, insn_rtor }, |
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286 { "sex", { 0x1d, -0x1, -0x1, -0x1 }, insn_inh }, |
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287 { "sexw", { 0x14, -0x1, -0x1, -0x1 }, insn_inh }, |
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288 { "sta", { 0x97, 0xa7, 0xb7, -0x1 }, insn_gen0 }, |
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289 { "stb", { 0xd7, 0xe7, 0xf7, -0x1 }, insn_gen0 }, |
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290 { "stbt", { 0x1137, -0x1, -0x1, -0x1 }, insn_bitbit }, |
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291 { "std", { 0xdd, 0xed, 0xfd, -0x1 }, insn_gen0 }, |
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292 { "ste", { 0x1197, 0x11a7, 0x11b7, -0x1 }, insn_gen0 }, |
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293 { "stf", { 0x11d7, 0x11e7, 0x11f7, -0x1 }, insn_gen0 }, |
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294 { "stq", { 0x10dd, 0x10ed, 0x10fd, -0x1 }, insn_gen0 }, |
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295 { "sts", { 0x10df, 0x10ef, 0x10ff, -0x1 }, insn_gen0 }, |
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296 { "stu", { 0xdf, 0xef, 0xff, -0x1 }, insn_gen0 }, |
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297 { "stw", { 0x1097, 0x10a7, 0x10b7, -0x1 }, insn_gen0 }, |
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298 { "stx", { 0x9f, 0xaf, 0xbf, -0x1 }, insn_gen0 }, |
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299 { "sty", { 0x109f, 0x10af, 0x10bf, -0x1 }, insn_gen0 }, |
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300 { "suba", { 0x90, 0xa0, 0xb0, 0x80 }, insn_gen8 }, |
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301 { "subb", { 0xd0, 0xe0, 0xf0, 0xc0 }, insn_gen8 }, |
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302 { "subd", { 0x93, 0xa3, 0xb3, 0x83 }, insn_gen16 }, |
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303 { "sube", { 0x1190, 0x11a0, 0x11b0, 0x1180 }, insn_gen8 }, |
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304 { "subf", { 0x11d0, 0x11e0, 0x11f0, 0x11c0 }, insn_gen8 }, |
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305 { "subr", { 0x1032, -0x1, -0x1, -0x1 }, insn_rtor }, |
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306 { "subw", { 0x1090, 0x10a0, 0x1090, 0x1080 }, insn_gen8 }, |
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307 { "swi", { 0x3f, -0x1, -0x1, -0x1 }, insn_inh }, |
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308 { "swi2", { 0x103f, -0x1, -0x1, -0x1 }, insn_inh }, |
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309 { "swi3", { 0x113f, -0x1, -0x1, -0x1 }, insn_inh }, |
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310 { "sync", { 0x13, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 311 |
312 // note: r+,r+ r-,r- r+,r r,r+ | |
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313 { "tfm", { 0x1138, 0x1139, 0x113a, 0x113b }, insn_tfm }, |
0 | 314 |
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315 { "tfr", { 0x1f, -0x1, -0x1, -0x1 }, insn_rtor }, |
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316 { "tim", { 0x0b, 0x6b, 0x7b, -0x1 }, insn_logicmem }, |
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317 { "tst", { 0x0d, 0x6d, 0x7d, -0x1 }, insn_gen0 }, |
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318 { "tsta", { 0x4d, -0x1, -0x1, -0x1 }, insn_inh }, |
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319 { "tstb", { 0x5d, -0x1, -0x1, -0x1 }, insn_inh }, |
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320 { "tstd", { 0x104d, -0x1, -0x1, -0x1 }, insn_inh }, |
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321 { "tste", { 0x114d, -0x1, -0x1, -0x1 }, insn_inh }, |
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322 { "tstf", { 0x115d, -0x1, -0x1, -0x1 }, insn_inh }, |
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323 { "tstw", { 0x105d, -0x1, -0x1, -0x1 }, insn_inh }, |
0 | 324 |
47
804d7465e0f9
Implemented ORG and fixed problems with constants using $, &, or @ to specify base
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325 { "org", { -1, -1, -1, -1 }, pseudo_org }, |
804d7465e0f9
Implemented ORG and fixed problems with constants using $, &, or @ to specify base
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326 |
63
d85ba47b1e8f
Moved symbol registration so symbols that are in skipped code do not get registered and so EQU/SET can do their own registration
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327 { "equ", { -1, -1, -1, -1 }, pseudo_equ, 0, 0, 1 }, |
d85ba47b1e8f
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328 { "=", { -1, -1, -1, -1 }, pseudo_equ, 0, 0, 1 }, |
82 | 329 { "extern", { -1, -1, -1, -1 }, pseudo_extern, 0, 0, 1 }, |
330 { "external", { -1, -1, -1, -1 }, pseudo_extern, 0, 0, 1 }, | |
90 | 331 { "import", { -1, -1, -1, -1 }, pseudo_extern, 0, 0, 1 }, |
332 { "export", { -1, -1, -1, -1 }, pseudo_export, 0, 0, 1 }, | |
82 | 333 |
50 | 334 |
335 { "rmb", { -1, -1, -1, -1 }, pseudo_rmb }, | |
53 | 336 { "rmd", { -1, -1, -1, -1 }, pseudo_rmd }, |
337 { "rmq", { -1, -1, -1, -1 }, pseudo_rmq }, | |
338 | |
54
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Fixed typo in instruction table and added END directive
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339 { "zmb", { -1, -1, -1, -1 }, pseudo_zmb }, |
360d53062bb9
Fixed typo in instruction table and added END directive
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340 { "zmd", { -1, -1, -1, -1 }, pseudo_zmd }, |
360d53062bb9
Fixed typo in instruction table and added END directive
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341 { "zmq", { -1, -1, -1, -1 }, pseudo_zmq }, |
360d53062bb9
Fixed typo in instruction table and added END directive
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342 |
56 | 343 { "fcc", { -1, -1, -1, -1 }, pseudo_fcc }, |
70
8aa6a28cba02
Fixed instruction table to vector to correct routines for fcn and fcs
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344 { "fcn", { -1, -1, -1, -1 }, pseudo_fcn }, |
8aa6a28cba02
Fixed instruction table to vector to correct routines for fcn and fcs
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345 { "fcs", { -1, -1, -1, -1 }, pseudo_fcs }, |
56 | 346 |
347 { "fcb", { -1, -1, -1, -1 }, pseudo_fcb }, | |
348 { "fdb", { -1, -1, -1, -1 }, pseudo_fdb }, | |
349 { "fqb", { -1, -1, -1, -1 }, pseudo_fqb }, | |
350 | |
54
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Fixed typo in instruction table and added END directive
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351 { "end", { -1, -1, -1, -1 }, pseudo_end }, |
50 | 352 |
52 | 353 { "include", { -1, -1, -1, -1 }, pseudo_include }, |
56 | 354 |
355 { "align", { -1, -1, -1, -1 }, pseudo_align }, | |
356 | |
357 { "error", { -1, -1, -1, -1}, pseudo_error }, | |
52 | 358 |
57 | 359 { "ifeq", { -1, -1, -1, -1}, pseudo_ifeq, 1 }, |
360 { "ifne", { -1, -1, -1, -1}, pseudo_ifne, 1 }, | |
361 { "if", { -1, -1, -1, -1}, pseudo_ifne, 1 }, | |
362 { "ifgt", { -1, -1, -1, -1}, pseudo_ifgt, 1 }, | |
363 { "ifge", { -1, -1, -1, -1}, pseudo_ifge, 1 }, | |
364 { "iflt", { -1, -1, -1, -1}, pseudo_iflt, 1 }, | |
365 { "ifle", { -1, -1, -1, -1}, pseudo_ifle, 1 }, | |
366 { "endc", { -1, -1, -1, -1}, pseudo_endc, 1 }, | |
367 { "else", { -1, -1, -1, -1}, pseudo_else, 1 }, | |
104 | 368 { "ifdef", { -1, -1, -1, -1}, pseudo_ifdef, 1}, |
369 { "ifndef", { -1, -1, -1, -1}, pseudo_ifndef, 1}, | |
57 | 370 |
67 | 371 { "macro", { -1, -1, -1, -1}, pseudo_macro, 1, 0, 1 }, |
372 { "endm", { -1, -1, -1, -1}, pseudo_endm, 1, 1, 1 }, | |
57 | 373 |
65
31d8e85706e7
Implemented setdp and corrected handling of direct page detection in insn_gen_aux()
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374 { "setdp", { -1, -1, -1, -1}, pseudo_setdp }, |
63
d85ba47b1e8f
Moved symbol registration so symbols that are in skipped code do not get registered and so EQU/SET can do their own registration
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375 { "set", { -1, -1, -1, -1}, pseudo_set, 0, 0, 1 }, |
d85ba47b1e8f
Moved symbol registration so symbols that are in skipped code do not get registered and so EQU/SET can do their own registration
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376 |
73 | 377 { "section", { -1, -1, -1, -1}, pseudo_section }, |
378 { "sect", { -1, -1, -1, -1}, pseudo_section }, | |
379 { "ends", { -1, -1, -1, -1}, pseudo_endsection }, | |
380 { "endsect", { -1, -1, -1, -1}, pseudo_endsection }, | |
381 { "endsection", { -1, -1, -1, -1}, pseudo_endsection }, | |
382 | |
383 { "pragma", { -1, -1, -1, -1}, pseudo_pragma }, | |
384 { "*pragma", { -1, -1, -1, -1}, pseudo_starpragma }, | |
385 | |
386 | |
0 | 387 /* flag end of table */ |
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388 { NULL, { -0x1, -0x1, -0x1, -0x1 }, insn_inh } |
0 | 389 }; |